Senior Silicon Design Verification Engineer, Cloud Silicon

About the job:
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities:
Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Measure to identify verification holes and to show progress towards tape-out.
Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).

Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.
Experience in verification and debug of IP/subsystem/SoCs in the networking domain such as packet processing, bandwidth management, congestion control.
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with industry-standard simulators, revision control systems, and regression systems.
Experience in Artificial Intelligence/Machine Learning (AI/ML) accelerators or vector processing units.
Experience with the full verification life cycle.
Excellent problem-solving and communication skills.