Design Verification Engineer, Cloud Silicon

About the job:
In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.

Responsibilities:
Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Measure to identify verification holes and to show progress towards tape-out.
Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).

Minimum qualifications:
Bachelor's degree in Electrical Engineering, or equivalent practical experience.
1 year of experience with verification methodology such as universal verification methodology (UVM).
1 year of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
Experience with SystemVerilog, SVA, and functional coverage.

Preferred qualifications:
Master's degree in Electrical Engineering, or a related technical field.
Experience with industry-standard simulators, revision control systems, and regression systems.
Experience with the full verification life-cycle.
Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units.
Excellent problem-solving and communication skills.