Responsibilities:
Define and drive to the implementation of physical design European Market Infrastructure Regulation (EMIR) methodologies.
Take ownership of EMIR of one or more physical design partitions or top level.
Drive to the closure of EMIR a of the SoC design.
Contribute to design methodology, libraries, and code review.
Define the physical design related rule sets for the functional design engineers.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
Experience with EMIR convergence on blocks/Sub-System (SS)/SoC.
Experience in automation and scripting with TCL/Python.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in coding with System Verilog and scripting with TCL.
Experience with Very Large Scale Integration (VLSI) design in SoC or multiple-cycles of SoC in Application-Specific Integrated Circuit (ASIC) design.
Experience with layout verification and design rules.
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