About the job:
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Responsibilities:
Work with a group of architecture and silicon engineers to develop next-generation DFT/DFX features for large-scale SoCs.
Design and implement software and hardware validation solutions for advanced testing, including logic BIST (LBIST), memory BIST (MBIST), and Scan compression.
Research, develop, and integrate machine learning or semi-analytical models to solve complex DFT challenges.
Triage, debug, and resolve high-priority post-silicon yield and structural failures by driving advanced failure analysis (FA) and volume diagnostics.
Write and review technical specifications for SoC testability and partner with EDA vendors.
Minimum qualifications:
PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience.
Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools.
Preferred qualifications:
2 years of experience in Silicon Engineering post PhD.
Experience with Electronic Design Automation (EDA) tools in design, verification, DFT and implementation.
Design for Test (DFT) knowledge (Boundary Scan, ATPG, MBIST).
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