Senior SOC Debug Verification Engineer

The candidate for this position will be expected and able to complete the following responsibilities: Own verification of Design for Debug (DFD) SoC level flows including Task planning and schedule estimation, proactively identifying and removing roadblocks and finding ways to make the team more efficient Develop verification strategy, requirements, environments, tools, and methodologies Become an proficient on the overall debug architecture, understand customer use models, and understand interactions with other parts of the SOC, with the platform, and with software Apply your knowledge of verification principles and techniques and your judgement to write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral Run tests, debug failures to root cause, and recommend fixes Apply your growth mindset to learn and adapt in a complex and dynamic environment Engage with partners to drive continuous improvement to both the design, to verification plans/collateral, and to methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise Delight your customers by providing high quality results on schedule Provide technical leadership with respect and integrity Apply your expertise towards supporting the post-silicon validation plans, tests, and debug of your area Apply industry leading generative AI solutions to verification work 8+ years of pre-silicon SOC or subsystem or IP verification experience. Candidate with least bachelor's or master's degree in electrical, Electronics, Computer Engineering, Computer Science or a related degree 6+ years of verification experience working on CPU/SOC designs, with 2+ years of design for debug verification experience Experience with SOC DFD verification for a full product cycle from definition to silicon, including writing SOC level test plans, developing tests, debugging failures and coverage signoff Demonstrated expertise in industry standard DFD architectural protocols such as JTAG interface, hardware triggers, breakpoints and tracing and hands-on experience in ARM Core Sight debug components (DAP, CTI ETIM, TPIU, Funnel/Replicators) Familiarity with ARM AMBA protocols (AXI/ACE/CHI preferred) Experience enabling and/or utilizing debug features in post-silicon Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams Experience planning verification tasks, estimating and assigning tasks, coordinating with customers and suppliers, and executing the plan Proficient leadership skills Passion for improving verification efficiency Experience with Agile software practices This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.