About the job:
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities:
Define and drive to the implementation of physical design STA methodologies.
Take ownership of Static Timing Analysis (STA) of one or more physical design partitions or top level.
Drive to the closure of timing and power consumption of the design.
Contribute to design methodology, libraries, and code review.
Define the physical design STA constraints rule sets for the Physical design engineers.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
3 years of experience in coding or scripting languages (e.g., Python, TCL).
3 years of experience in physical design flows and methodologies, with focus on STA (timing analysis).
Experience with high-speed design timing convergence and Static Timing Analysis (STA) tools (e.g., PrimeTime, Tempus).
Experience with Engineering Change Order (ECO) flows.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with scripting languages such as Perl, Python, or Tcl.
Experience with constraints, synthesis or clock tree synthesis (CTS).
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