DDR Design Verification Lead Engineer

Company:
Qualcomm India Private Limited

Job Area:
Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

Job Overview

We are looking to hire a strong DV engineer to work on verification of LPDDR/DDR based IPs and Subsystems in the Infra IP team

• Create DV infrastructure for verification
• Integrate VIP's
• Create and execute test plans, debug failures, write assertions, close code and functional coverage
• Ensure high quality verification
• Working with all stakeholders to ensure program success

Minimum Qualifications

Bachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field.

11+ years Hardware Engineering experience or related work experience.

Preferred Qualifications

Following skill set is required:
• Strong Debug, UVM, System Verilog
• Understanding Specs and Standards and developing relevant test plans
• Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved
• Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening
• Preferred Qualifications 4+ Year of industry experiences in the following areas: -
• Thorough understanding of Digital design concepts
• Thorough understanding dv methodologies and tools
• Good understanding of DDR/LPDDR families (LP/PC) and generations (DDR2/3/4/5)
• Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite

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