About the job:
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities:
Lead technical evaluations of advanced process nodes and drive the strategy for custom circuits and memories/SRAMs to hit dynamic PPA targets.
Engage with foundry partners to receive and debug necessary collaterals for design kits, standard cells, memories, other IPs, and more.
Provide technical mentorship and guidance to circuit and physical design teams, overseeing the design and verification of custom circuits. Drive circuit level assessments of performance and power metrics.
Define optimal methodologies by investigating performance, power, and area across different technology nodes and implementation techniques. Drive library cell and metal interconnect analysis and enhancements for improving PPA.
Collaborate with our circuits, physical design, logic design, and technology teams in advanced CMOS nodes to ensure standard cell libraries and memories/SRAMs are seamlessly integrated. Evaluate impact due to new PDK releases.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
15 years of experience in process technology, circuit design, and physical design.
Experience in process technology nodes, including yield and reliability, design kit, IP collaterals, and evaluating power, performance, and area.
Experience in transistor level design in finfet nodes for standard cells, and memories/SRAMs, including SPICE simulations or characterization methodology.
Experience with concurrent optimization across custom circuit/IP and physical design spaces.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering.
Experience with programming/scripting (Python, TCL).
Proven track record of technical leadership, guiding teams through design and tapeout and interfacing with foundry suppliers.
Strong understanding of semiconductor device physics and transistor characteristics.
Track record of delivering circuit and physical design solutions, including across standard cells and memories/SRAMs, leading to product tapeout.
Strong documentation, presentation, and communication skills.
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