About the job:
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities:
Define and drive to the implementation of physical design and physical verification (PV) methodologies.
Take ownership of PV of one or more physical design partitions or top level.
Drive to the closure of PV of the SoC design.
Contribute to design methodology, libraries, and code review.
Define the physical design rule sets for the physical design engineers.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with physical design verification flows and methodology such as DRC, LVS, PERC, ESD signoff, ERC, antenna, DFM, or dummyfill checks, using industry standard signoff tools (e.g., Calibre).
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with scripting languages such as Perl, Python, or Tcl.
Experience with constraints, synthesis or clock tree synthesis (CTS).
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