Digital Design Engineer, RTL IP, Silicon

About the job:
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities:
Work on both IP design and integration activities including: plan tasks, support, hold code and design reviews, contribute on sub-system/chip-level integration.
Interact closely with the architecture team and develop implementation strategies to meet the quality, schedule, and power performance area for Internet Protocols (IPs).
Interact closely with the subsystem team and plan SOC milestones, plan quality checks as part of System-on-Chip (SOC) milestones (e.g., IPXACT, Control and Status Register (CSR), Lint, Clock Domain Crossing (CDC), Synopsys Design Constraints (SDC), Unified Power Format (UPF), etc.).
Work closely with cross-functional teams of verification, design for test, physical design, emulation, and software to make design decisions and represent project status throughout the development process.

Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages, such as Verilog or SystemVerilog.
Experience with bus protocols such as Advanced Extensible Interface (AXI), Coherent Hub Interface (CHI), AXI Coherency Extensions (ACE) Lite.
Experience with multiple SoCs with silicon success and with chip design flow.

Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
Experience in micro-architecture and coding in one or more of these areas: memory compression, interconnects, coherence, cache.
Experience working with the internals of Network-on-Chip (NoC).
Domain knowledge and expertise with ARM based SoC, Debug (e.g., coresight).
Understanding of cross-domain involving domain validation, design for testing, physical design, and software.
Proficiency with Application-Specific Integrated Circuit (ASIC) design methodologies for front quality checks like; Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation.