Physical Design and Implementation Engineer, ASIC

About the job:
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities:
Develop high-performance hardware and software to enable Google’s continuous innovations in working with Application Specific Integrated Circuits (ASIC) as a physical design and implementation engineer.
Collaborate with architects and logic designers to initiate architectural feasibility studies, establish timing, power, and area design objectives, and investigate Register Transfer Language (RTL)/design trade-offs for physical design closure.
Work with verification and software teams to comprehend and execute the design requirements for clocking and power management.
Develop all aspects of ASIC RTL2GDS implementation for high PPA designs.
Manage block and sub-system level physical implementation and QoR (power, timing, area).

Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience in Physical Design.
Experience in high performance synthesis, PnR and sign-off optimizations, sign-off convergence, including Static Timing Analysis (STA), electrical checks and physical verification.
Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).

Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Knowledge of Verilog/SystemVerilog.
Understanding of circuit design, device physics and deep submicron technology.
Excellent scripting skills with languages such as Python, Tcl, or Perl.