Principal Silicon Engineer

Take ownership and responsibility for our fullchip/package integration Take an active role in early-phase design planning with die size planning, floorplanning, C4/microbump development, and RDL insertion & optimization Develop, enhance, and maintain full-chip integration methodologies; collaborate with vendors and partners to align workflows with industry practices, address tool-related issues, and improve the reliability and efficiency of full-chip finishing and integration processes. Define & drive to integration milestones across project phases; manage interaction and integration with package team & vendors to ensure continuity of entire system design Manage multiple power domains & islands, ensuring correctness and robustness of the design Ensure a convergent integration process and drive package closure through all phases including final signoff for tapeout Work across teams to identify and resolve power delivery issues, integration issues, etc; provide guidance for floorplan adjustments to address power integrity issues and continuity of the package and board design Bachelor's degree in computer engineering, electrical engineering, or related field 7+ years of physical design experience with focus on C4 integration & chip finishing Experience with ASIC design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime) & Physical Verification tools (e.g., Calibre) 10+ years of hands-on physical design experience with focus on C4/RDL integration, chip finishing, and signoff Deep expertise in power planning, C4/microbump deployment and chip/package interfaces Proficiency in flow automation, scripting (TCL/Perl) & tool debug Ability to develop & maintain package signoff checklists, to track and report fullchip integration progress through all design phases, and successfully execute chip closure on schedule Demonstrated tapeout experience in TSMC 5nm process or below